
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 143
PIC18FXX39
FIGURE 16-11:
I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSP
IF
BF
(
S
PST
A
T
<
0>)
S
1
2
3
4
56
7
8
9
1
23
4
5
6
7
89
1
2
3
4
5
7
8
9
P
11
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
0
A
8
R/W=
1
AC
K
AC
K
R/W
=
0
ACK
R
eceive
F
ir
st
B
yte
of
A
d
dr
ess
Cle
a
re
d
in
so
ftwa
re
B
u
sM
aster
term
inates
tran
sfer
A9
6
(P
IR
1<
3>
)
R
e
ce
iv
eS
econd
B
yte
of
A
ddre
ss
C
le
ar
ed
by
hard
w
are
w
hen
S
P
A
D
is
u
pdate
d
w
ith
lo
w
byte
of
ad
dress
UA
(
S
PST
A
T
<1
>)
Clo
ck
is
h
e
ld
lo
w
u
ntil
up
date
o
fS
S
P
A
D
ha
s
ta
ken
place
UA
is
se
tindicatin
g
that
the
S
P
A
D
need
sto
be
upda
ted
UA
is
set
indicating
that
S
P
A
D
need
sto
be
update
d
Cle
ar
e
d
b
yh
a
rd
wa
re
wh
e
n
SSP
ADD
is
u
p
d
at
e
d
with
h
ig
h
by
te
o
fad
d
res
s
SS
PBUF
is
wr
itte
n
with
cont
ent
sof
S
P
S
R
Du
m
yr
ea
d
o
fSSP
BUF
to
cle
a
rB
F
fl
ag
Receive
F
irst
B
yte
of
A
d
dre
ss
12
3
4
5
7
8
9
D
7
D6
D5
D4
D3
D
1
AC
K
D2
6
T
ran
smitting
D
ata
B
yt
e
D0
D
u
mm
yre
ad
of
S
P
B
U
F
to
cle
a
rB
F
fl
ag
Sr
Cle
ar
e
d
in
so
ftwa
re
W
rit
eo
fSS
PBUF
in
itia
te
str
an
sm
it
C
lea
re
di
n
s
o
ft
w
a
re
Co
m
p
le
tio
n
o
f
clear
sB
F
flag
C
KP
(
SSP
CO
N<4
>
)
CK
P
is
set
in
software
CK
P
is
a
u
to
m
a
tica
lly
cl
ea
re
din
h
a
rd
wa
re
h
o
ld
in
gS
C
Llo
w
Clo
ck
is
h
e
ld
lo
w
u
n
til
upd
ate
of
S
P
A
D
has
ta
ken
p
lace
da
ta
tran
smission
Clo
ck
is
h
e
ld
lo
w
u
ntil
CK
P
is
set
to
‘1
’
B
F
fl
ag
is
clear
th
ir
d
ad
dress
s
e
quen
ce
at
the
e
n
d
of
th
e